1. Field of the Invention
This invention pertains to a buffer circuit for use in buffering data in a digital apparatus, such as a computer and a communications device.
2. Description of the Related Arts
Generally, because a digital apparatus, e.g. a computer and a communications device, adopts a method by which a required result is obtained by sequentially processing a series of data, its buffer circuit for buffering data must preserve an input/output sequence of the series of data in a predetermined format. Thus, an actual buffer circuit of a digital apparatus uses a FIFO (first-in, first-out) buffer or a LIFO (last-in, first-out) buffer.
However, this principle applies only to a generic digital apparatus, since there are cases in which a logical simulation apparatus for simulating the operation of a logical circuit need not preserve an input/output sequence of a series of data, in buffering a series of data, which are grouped together. The following is a description of a case in which a digital apparatus need not preserve an input/output sequence of a series of data, with reference to an outline of the operation and configuration of a conventional logical simulation apparatus.
FIG. 1 is a block diagram outlining the circuit configuration of a conventional generic logical simulation apparatus.
Japanese patent application publication circulars 1988-204441 and 1992-3229 concretely disclose the conventional generic logical simulation apparatus shown in FIG. 1.
The conventional generic logical simulation apparatus comprises a fan-out pipeline 1, an evaluation pipeline 2, a first evaluation gate memory (EGM1) 3, a second evaluation gate memory (EGM2) 4, a new event memory (NEM) 5, a net status memory (NSM) 6 and a fan-out buffer 7.
The conventional generic logical simulation apparatus comprises a communications network 8 for mutual communications, upon each evaluation of a gate group of a unit by a simulation apparatus operating in parallel with other plural logical simulation apparatuses having the same configuration, where a unit is defined as a minimum circuit unit configuring a combination circuit but not configuring a sequence circuit.
The fan-out pipeline 1 searches the gates at fan-out destinations of a particular gate whose output value changes in correspondence with the change of its input value, of the gates included in a gate group of a unit of a logical circuit. It supplies to the first evaluation gate memory (EGM1) 3 or the second evaluation gate memory (EGM2) 4 gate numbers assigned to the searched gates at the fan-out destinations as gate data.
The evaluation pipeline 2 evaluates whether or not the output values of the gates at the fan-out destinations change in correspondence with their input values, based on the gate data stored in the first evaluation gate memory (EGM1) 3 or the second evaluation gate memory (EGM2) 4. It supplies as new event data a gate number to the gate whose output value has changed of the evaluated gates at the fan-out destinations simultaneously to the new event memory (NEM) 5 and the fan-out buffer 7. It determines the output value of a gate whose input value has changed, on receiving from the net status memory (NSM) 6 status data on a desired gate.
The new event memory (NEM) 5 stores as new event data event data on a gate that changes its output value at a timing t, based on the evaluation result by the evaluation pipeline 2 at a timing t-1.
The net status memory (NSM) 6 stores status data on a gate which a processor evaluates.
The first evaluation gate memory (EGM1) 3 and the second evaluation gate memory (EGM2) 4 alternately input and output gate data at each timing in the above operation. For example, when the first evaluation gate memory (EGM1) 3 has received gate data from the fan-out pipeline 1 at timing t, the second evaluation gate memory (EGM2) 4 outputs to the evaluation pipeline 2 gate data received at timing t-1; and when the second evaluation gate memory (EGM2) 4 has received gate data from the fan-out pipeline 1 at a timing t+1, the first evaluation gate memory (EGM1) 3 outputs to the evaluation pipeline 2 gate data received at timing t.
While the first evaluation gate memory (EGM1) 3 and the second evaluation gate memory (EGM2) 4 repeat the alternate processes of an input and an output of gate data, the evaluation pipeline 2 generates new event data. As a result, when the new event memory (NEM) 5 stores a complete set of new event data on a gate group of a single particular unit belonging to a system composed of plural units, the net status memory (NSM) 6 changes to net status data of a gate group of a single unit to be evaluated next, its content supplied to the evaluation pipeline 2, in accordance with the complete set of new event data.
On the other hand, when the fan-out pipeline 1 has not completed searching the gates at the fan-out destinations of a gate included in the gate group of a single unit currently processed, the fan-out buffer 7 temporarily stores new event data supplied from the evaluation pipeline 2 to the fan-out buffer 7, and outputs them to the fan-out pipeline 1 only after the fan-out pipeline 1 completes searching the gates at the fan-out destinations. The fan-out pipeline 1 searches a gate of the fan-out destination of a gate group of the same single unit, based on the gate numbers included in the new event data.
That is, because the fan-out pipeline 1 searches a plurality of gates at fan-out destinations, it may take a longer time for the fan-out pipeline 1 to search for the plurality of gates at the fan-out destinations than a time for the evaluation pipeline 2 to evaluate the output values of the gates at the fan-out destinations. Thus, the fan-out buffer 7 buffers new event data to absorb this time difference.
The conventional generic logical simulation apparatus may have the fan-out pipeline 1 search in any sequence the gates at the fan-out destinations of the gate group of a single unit. A search of the gates at the fan-out destinations of the gate group of a single unit in a different sequence causes no change in a simulation result. This is because the gates belonging to the gate group of a single unit do not constitute a sequence circuit. Accordingly, the fan-out buffer 7 by no means needs to preserve their input/output sequence in buffering new event data. Instead, it is preferable for the fan-out buffer 7 to reduce a duration for buffering new event data by changing their input/output sequence, thereby enhancing a processing efficiency.
However, because the fan-out buffer 7 uses a general-purpose buffer circuit such as a FIFO buffer, the fan-out buffer 7 outputs to the fan-out pipeline 1 new event data inputted from the evaluation pipeline 2 in their input sequence. Hence, the conventional generic logical simulation apparatus must provide for the fan-out buffer 7 two 2! counters for writing and reading new event data. Besides, the conventional generic logical simulation apparatus may not read out from the fan-out buffer 7 new event data to be outputted to the fan-out pipeline 1, while writing into the fan-out pipeline 1 new event data being inputted from the evaluation pipeline 2.
That is, the conventional generic logical simulation apparatus has a problem of putting on hold a readout (output) of new event data from the fan-out buffer 7 to the fan-out pipeline 1, during a write-in (input) of new event data from the evaluation pipeline 2 to the fan-out buffer 7.